1. Technical Field of the Invention
The present invention relates to the field of integrated circuit, and more particularly to three-dimensional one-time-programmable memory (3D-OTP).
2. Prior Arts
Three-dimensional memory (3D-M) is a monolithic semiconductor memory comprising a plurality of vertically stacked memory cells. It includes three-dimensional read-only memory (3D-ROM) and three-dimensional random-access memory (3D-RAM). The 3D-ROM can be further categorized into three-dimensional mask-programmed read-only memory (3D-MPROM) and three-dimensional electrically-programmable read-only memory (3D-EPROM). Depending on the number of times it can be electrically programmed, 3D-EPROM can be further categorized into three-dimensional one-time-programmable memory (3D-OTP) and three-dimensional multiple-time-programmable memory (3D-MTP). 3D-M may be a 3D-memristor, 3D-RRAM or 3D-ReRAM (resistive random-access memory), 3D-PCM (phase-change memory), 3D-PMC (programmable metallization-cell memory), or 3D-CBRAM (conductive-bridging random-access memory).
U.S. Pat. No. 5,835,396 issued to Zhang on Nov. 3, 1998 discloses a 3D-ROM, more particularly a 3D-OTP. As illustrated in FIG. 1A, a 3D-OTP die 20 comprises a substrate circuit 0K and a plurality of vertically stacked memory levels 16A, 16B. The substrate circuit 0K comprises transistors 0t and interconnects 0i. In this example, the interconnects 0i include metal levels 0M1, 0M2. Hereinafter, the metal levels 0M1, 0M2 in the interconnects 0i are referred to as interconnect levels; the materials used in the interconnects 0i are referred to as interconnect materials.
The memory levels 16A, 16B are stacked above the substrate circuit 0K. They are coupled to the substrate 0 through contact vias (e.g. 1av). Each of the memory levels (e.g. 16A) comprises a plurality of upper address lines (e.g. 2a), lower address lines (e.g. 1a) and memory cells (e.g. 1aa). The memory cells could comprise diodes, transistors or other devices. Among all types of memory cells, the diode-based memory cells are of particular interest because they have the smallest size of ˜4 F2, where F is the minimum feature size. Since they are generally located at the cross points between the upper and lower address lines, the diode-based memory cells form a cross-point array. Hereinafter, diode is broadly interpreted as any two-terminal device whose resistance at the read voltage is substantially lower than when the applied voltage has a magnitude smaller than or polarity opposite to that of the read voltage. In other disclosures, diode is also referred to as steering device or selection device. In one exemplary embodiment, diode is a semiconductor diode, e.g. p-i-n silicon diode. In another exemplary embodiment, diode is a metal-oxide diode, e.g. titanium-oxide diode, nickel-oxide diode.
The memory levels 16A, 16B collectively form at least a 3D-OTP array 16, while the substrate circuit 0K comprises the peripheral circuit for the 3D-OTP array 16. A first portion of the peripheral circuit is located underneath the 3D-OTP array 16 and it is referred to as under-array peripheral circuit. A second portion of the peripheral circuit is located outside the 3D-OTP array 16 and it is referred to as outside-array peripheral circuits 18. Because the outside-array peripheral circuit 18 generally comprises fewer back-end-of-line (BEOL) levels than the 3D-OTP array 16, the space 17 above the outside-array peripheral circuits 18 is empty and completely wasted. Hereinafter, a BEOL level refers to a level of conductive lines above the substrate, e.g. an address-line level in the memory levels 16A, 16B; or, an interconnect level in the interconnects 0i. In FIG. 1A, the 3D-OTP array 16 comprises a total of six BEOL levels, including the two interconnect levels 0M1, 0M2, two address-line levels 1a, 2a for the first memory level 16A, and two address-line levels 3a, 4a for the second memory level 16B. The outside-array peripheral circuit 18 comprises only two BEOL levels, i.e. the interconnect levels 0M1, 0M2.
U.S. Pat. No. 7,383,476 issued to Crowley et al. on Jun. 3, 2008 discloses an integrated 3D-OTP die, whose 3D-OTP arrays and peripheral circuit are integrated into a single die. Generally, this design methodology is known as full integration. As is illustrated in FIG. 1B, an integrated 3D-OTP die 20 comprises a 3D-array region 22 and a peripheral-circuit region 28. The 3D-array region 22 comprises a plurality of 3D-OTP arrays (e.g. 22aa, 22ay) and their decoders (e.g. 24, 24G). These decoders include local decoders 24 and global decoders 24G. The local decoder 24 decodes address/data for a single 3D-OTP array, while the global decoder 24G decodes global address/data 25 to each 3D-OTP array.
The peripheral-circuit region 28 comprises all necessary peripheral-circuit components for a standalone integrated 3D-OTP die 20 to perform basic memory functions, i.e. it can directly use the voltage supply 23 provided by a user (e.g. a host device or a controller), directly read and/or write data 27 for the user. It includes a read/write-voltage generator (VR/VW-generator) 21 and an address/data (A/D)-translator 29. The VR/VW-generator 21 provides read voltage VR and/or write (programming) voltage VW to the 3D-OTP array(s). The A/D-translator 29 converts address and/or data from a logical space to a physical space and/or vice versa. Hereinafter, the logical space is the space viewed from the perspective of a user of the 3D-OTP, while the physical space is the space viewed from the perspective of the 3D-OTP.
It is a prevailing belief in the field of integrated circuit that more integration is better, because integration lowers cost, improves performance and reduces size. However, this belief is no longer true for 3D-OTP. As the 3D-OTP 20 is optimized for the 3D-OTP array 16, the cost, performance and size of the peripheral circuit 18 are sacrificed. First of all, because the 3D-OTP array 16 comprises significantly more BEOL levels than the peripheral circuit 18, full integration would force a relatively simple peripheral circuit 18 to use the expensive BEOL manufacturing process of the 3D-OTP array 16. This increases the overall 3D-OTP cost. Secondly, because it comprises only a small number of interconnect levels (two in FIG. 2), the peripheral circuit 18 is difficult to design, have a poor performance and occupy a large area. Thirdly, full integration would force the peripheral circuit 18 to use the same high-temperature interconnect materials (e.g. tungsten and/or silicon oxide) as the 3D-OTP array 16. These materials slow down the peripheral circuit 18 and in turn, degrade the overall 3D-OTP performance.